Modern computer systems employ processors which are capable of operating at much higher rates of execution than large capacity main memories can support, and a low capacity high-speed cache memory is commonly used in addition to a large capacity main memory to improve program execution speed. The cache memory stores a limited number of instruction or data words; and for each memory read operation, the cache memory is checked to determine if the information is available in the cache memory. If the information is there, it will be read from cache memory; otherwise, it will be read from the main memory. Memory write operations generally cause information to be written simultaneously into the cache and the main memory. The processor normally addresses the main and cache memories using a virtual address defining a relative memory location. A real address defining an actual memory location is derived from the virtual address by an address translation buffer. The most significant bits of the virtual address, which are the segment and page address bits, are translated by the address translation buffer. The least significant address bits of the virtual address, which are the word address bits, are not translated but are directly used by the memory. These word address bits define the page size of the system.
The cache control circuit may use either a purely associative or a set associative technique, to determine if the accessed word is in the cache memory. In a cache memory using the set associative tecnhique, a data memory stores information words (data and instruction words), and a tag memory stores tag address words which define the locations in main memory where corresponding information words are stored. The word address bits define the word to be accessed in both the data and tag memories. When the cache memory is accessed, an information word is read from the data memory and simultaneously a tag address word is read from the tag memory. The tag address word is compared with the real address bits from the address translation buffer to determine if a match has occurred indicating that the information word is the desired word. The occurrence of a match is commonly called a hit, and the hit ratio is the ratio of matches to read operations. The performance is increased by increasing the hit ratio. The performance of a cache memory depends not only on the number of words contained in the cache memory, but also on how the cache memory is structured in comparison to the address translation buffer.
Since the size of both the page and cache memory is determined by the number of word address bits, the number of cache memory words generally equals the number of memory words in a page. A small page size is desirable in order to make the most efficient use of the main memory and the processor in a virtual address environment in which a number of different programs and data sets are simultaneously present in main memory. The smaller page simplifies the problem of allocating memory space between the different programs and data sets and this results in less processor time being used for this operation. Memory is used more efficiently because the smaller page size allows the memory space allocated to more closely approximate the amount required in each memory allocation operation. In a cache memory, it is also desirable to have the maximum number of cache memory words in order to achieve a high-hit ratio per memory access. In addition, a cache memory organization having a large number of words takes advantage of high density memory chips which are organized to have a large number of words, but have a small number of bits per word. Hence, the requirement that the page size equal the cache memory size results in an inefficient design with respect to either the page or cache memory size or both.